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| author | Raul E Rangel <rrangel@chromium.org> | 2021-04-30 10:42:18 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-05-03 19:10:00 +0000 |
| commit | ab8cc142a727c917aa58bd3ff1e3097332ee2610 (patch) | |
| tree | 76e41f42e41aa2642b7e5f9b9d35be52d7d7171b /src/cpu/intel/speedstep | |
| parent | b1623f23c0095a7dce6c874271f977f197f4949e (diff) | |
mb/google/mancomb: Fix S0i3/S3 GPIO configuration
Using PAD_WAKE is actually wrong. The wake bits are only supposed to be
set when using the GPIO controller to wake the system. coreboot's
current architecture relies on using GPEs to wake the system.
BUG=b:186011392
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib956fc299fe21cd7ea0b465cbdc5c8da830a668d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/cpu/intel/speedstep')
0 files changed, 0 insertions, 0 deletions