Overhaul speedstep code

This adds proper support for turbo and super-low-frequency modes.
Calculation of the p-states has been rewritten and moved into an
extra file speedstep.c so it can be used for non-acpi stuff like
EMTTM table generation.

It has been tested with a Core2Duo T9400 (Penryn) and a Core Duo T2300
(Yonah) processor.

Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1658
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 115 insertions, 80 deletions

diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 070f8d5076..910055d443 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2009 coresystems GmbH
+ *               2012 secunet Security Networks AG
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -28,7 +29,18 @@
 #include <cpu/intel/speedstep.h>
 #include <device/device.h>
 
-// XXX: PSS table values for power consumption are for Merom only
+/**
+ * @brief Returns c-state entries for this system
+ *
+ * This function is usually overwritten in mainboard code.
+ *
+ * @return Number of c-states *entries will point to.
+ */
+int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries
+					  __attribute__((unused)))
+{
+	return 0;
+}
 
 static int determine_total_number_of_cores(void)
 {
@@ -47,110 +59,133 @@ static int determine_total_number_of_cores(void)
 	return count;
 }
 
+/**
+ * @brief Returns three times the FSB clock in MHz
+ *
+ * The result of calculations with the returned value shall be divided by 3.
+ * This helps to avoid rounding errors.
+ */
 static int get_fsb(void)
 {
 	const u32 fsbcode = rdmsr(0xcd).lo & 7;
 	switch (fsbcode) {
-		case 0: return 266;
-		case 1: return 133;
-		case 2: return 200;
-		case 3: return 166;
-		case 4: return 333;
-		case 5: return 100;
-		case 6: return 400;
+		case 0: return  800; /*  / 3 == 266 */
+		case 1: return  400; /*  / 3 == 133 */
+		case 2: return  600; /*  / 3 == 200 */
+		case 3: return  500; /*  / 3 == 166 */
+		case 4: return 1000; /*  / 3 == 333 */
+		case 5: return  300; /*  / 3 == 100 */
+		case 6: return 1200; /*  / 3 == 400 */
 	}
-	printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n");
-	return 200;
+	printk(BIOS_WARNING,
+	       "Warning: No supported FSB frequency. Assuming 200MHz\n");
+	return 600;
 }
 
-int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries __attribute__((unused)))
+static int gen_pstate_entries(const sst_table_t *const pstates,
+			      const int cpuID, const int cores_per_package,
+			      const uint8_t coordination)
 {
-	return 0;
+	int i;
+	int len, len_ps;
+	int frequency;
+
+	len = acpigen_write_empty_PCT();
+	len += acpigen_write_PSD_package(
+			cpuID, cores_per_package, coordination);
+	len += acpigen_write_name("_PSS");
+
+	const int fsb3 = get_fsb();
+	const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO(
+		pstates->states[pstates->num_states - 1]);
+	const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(pstates->states[0]);
+	printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n",
+	       (min_ratio2 * fsb3)
+		/ (pstates->states[pstates->num_states - 1].is_slfm ? 12 : 6),
+	       (max_ratio2 * fsb3) / 6);
+
+	printk(BIOS_DEBUG, "adding %x P-States between "
+			   "busratio %x and %x, ""incl. P0\n",
+	       pstates->num_states, min_ratio2 / 2, max_ratio2 / 2);
+	len_ps = acpigen_write_package(pstates->num_states);
+	for (i = 0; i < pstates->num_states; ++i) {
+		const sst_state_t *const pstate = &pstates->states[i];
+		/* Report frequency of turbo mode as that of HFM + 1. */
+		if (pstate->is_turbo)
+			frequency = (SPEEDSTEP_DOUBLE_RATIO(
+					pstates->states[i + 1]) * fsb3) / 6 + 1;
+		/* Super-LFM runs at half frequency. */
+		else if (pstate->is_slfm)
+			frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/12;
+		else
+			frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/6;
+		len_ps += acpigen_write_PSS_package(
+			frequency, pstate->power, 0, 0,
+			SPEEDSTEP_ENCODE_STATE(*pstate),
+			SPEEDSTEP_ENCODE_STATE(*pstate));
+	}
+	len_ps--;
+	acpigen_patch_len(len_ps);
+
+	len += acpigen_write_PPC(0);
+
+	len += len_ps;
+
+	return len;
 }
 
+/**
+ * @brief Generate ACPI entries for Speedstep for each cpu
+ */
 void generate_cpu_entries(void)
 {
-	int len_pr, len_ps;
+	int len_pr;
 	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
-	msr_t msr;
 	int totalcores = determine_total_number_of_cores();
 	int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
-	int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout
-	int count;
-	acpi_cstate_t *cst_entries;
+	int numcpus = totalcores/cores_per_package; /* This assumes that all
+						       CPUs share the same
+						       layout. */
+	int num_cstates;
+	acpi_cstate_t *cstates;
+	sst_table_t pstates;
+	uint8_t coordination;
+
+	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
+	       numcpus, cores_per_package);
 
-	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
+	num_cstates = get_cst_entries(&cstates);
+	speedstep_gen_pstates(&pstates);
+	if (((cpuid_eax(1) >> 4) & 0xffff) == 0x1067)
+		/* For Penryn use HW_ALL. */
+		coordination = HW_ALL;
+	else
+		/* Use SW_ANY as that was the default. */
+		coordination = SW_ANY;
 
-	for (cpuID=1; cpuID <=numcpus; cpuID++) {
+	for (cpuID = 0; cpuID < numcpus; ++cpuID) {
 		for (coreID=1; coreID<=cores_per_package; coreID++) {
 			if (coreID>1) {
 				pcontrol_blk = 0;
 				plen = 0;
 			}
+
+			/* Generate processor \_PR.CPUx. */
 			len_pr = acpigen_write_processor(
-					(cpuID - 1) * cores_per_package + coreID - 1, pcontrol_blk, plen);
-			len_pr += acpigen_write_empty_PCT();
-			len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
-			if ((count = get_cst_entries(&cst_entries)) > 0)
-				len_pr += acpigen_write_CST_package(cst_entries, count);
-			len_pr += acpigen_write_name("_PSS");
-
-			int max_states=8;
-			int busratio_step=2;
-			msr = rdmsr(IA32_PERF_STS);
-			int busratio_min=(msr.lo >> 24) & 0x1f;
-			int busratio_max=(msr.hi >> (40-32)) & 0x1f;
-			int vid_min=msr.lo & 0x3f;
-			msr = rdmsr(IA32_PLATFORM_ID);
-			int vid_max=msr.lo & 0x3f;
-			int clock_max=get_fsb()*busratio_max;
-			int clock_min=get_fsb()*busratio_min;
-			printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", clock_min, clock_max);
-#define MEROM_MIN_POWER 16000
-#define MEROM_MAX_POWER 35000
-			int power_max=MEROM_MAX_POWER;
-			int power_min=MEROM_MIN_POWER;
-
-			int num_states=(busratio_max-busratio_min)/busratio_step;
-			while (num_states > max_states-1) {
-				busratio_step <<= 1;
-				num_states >>= 1;
-			}
-			printk(BIOS_DEBUG, "adding %x P-States between busratio %x and %x, incl. P0\n",
-				num_states+1, busratio_min, busratio_max);
-			int vid_step=(vid_max-vid_min)/num_states;
-			int power_step=(power_max-power_min)/num_states;
-			int clock_step=(clock_max-clock_min)/num_states;
-			len_ps = acpigen_write_package(num_states + 1); /* For Super LFM, this must
-									   be increases by another one. */
-			len_ps += acpigen_write_PSS_package(
-					clock_max /*mhz*/, power_max /*mW*/, 0 /*lat1*/, 0 /*lat2*/,
-					(busratio_max << 8) | vid_max /*control*/,
-					(busratio_max << 8) | vid_max /*status*/);
-
-			int current_busratio=busratio_min+((num_states-1)*busratio_step);
-			int current_vid=vid_min+((num_states-1)*vid_step);
-			int current_power=power_min+((num_states-1)*power_step);
-			int current_clock=clock_min+((num_states-1)*clock_step);
-			int i;
-			for (i=0;i<num_states; i++) {
-				len_ps += acpigen_write_PSS_package(
-						current_clock /*mhz*/, current_power /*mW*/,
-						0 /*lat1*/, 0 /*lat2*/,
-						(current_busratio << 8) | current_vid /*control*/,
-						(current_busratio << 8) | current_vid /*status*/);
-				current_busratio -= busratio_step;
-				current_vid -= vid_step;
-				current_power -= power_step;
-				current_clock -= clock_step;
-			}
-			len_ps--;
-			acpigen_patch_len(len_ps);
-			len_pr += acpigen_write_PPC(0);
-			len_pr += len_ps;
+					cpuID * cores_per_package + coreID - 1,
+					pcontrol_blk, plen);
+
+			/* Generate p-state entries. */
+			len_pr += gen_pstate_entries(&pstates, cpuID,
+					cores_per_package, coordination);
+
+			/* Generate c-state entries. */
+			if (num_cstates > 0)
+				len_pr += acpigen_write_CST_package(
+							cstates, num_cstates);
+
 			len_pr--;
 			acpigen_patch_len(len_pr);
 		}
 	}
 }
-