diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-02-28 14:01:34 +0200 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-04-02 21:13:26 +0200 |
| commit | abdf15f40b1e0838a43a54704ba5277c8210d69f (patch) | |
| tree | 0dcf0ca40cc6a85df79fabaaab8748e59a018ad7 /src/cpu/intel/socket_mPGA604/Kconfig | |
| parent | afd141d5043b4e1489c4e4796fc50c43ef9b23e2 (diff) | |
Apply cache-as-ram conditionally on socket mPGA604
The socket mPGA604 is for P4 Xeon which to my knowledge is always
HT-enabled. I assume the existing usage of car/cache_as_ram.inc
on socket_mPGA604, namely the Tyan S2735, as broken.
Existing car/cache_as_ram.inc has invalid SIPI vector and it does
not initialise AP CPU's to activate L2 cache.
Other mPGA604 boards are not affected, as they have not been
converted to CAR.
Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/607
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/socket_mPGA604/Kconfig')
| -rw-r--r-- | src/cpu/intel/socket_mPGA604/Kconfig | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 2fc27cff78..4fa7569d85 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,5 +1,10 @@ config CPU_INTEL_SOCKET_MPGA604 bool + +if CPU_INTEL_SOCKET_MPGA604 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y select CPU_INTEL_MODEL_F2X select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X @@ -13,4 +18,14 @@ config CPU_INTEL_SOCKET_MPGA604 config SSE2 bool default n - depends on CPU_INTEL_SOCKET_MPGA604 + +config DCACHE_RAM_BASE + hex + default 0x0ffafc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +endif # CPU_INTEL_SOCKET_MPGA604 + |