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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-03 10:39:16 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-05 07:48:58 +0000 |
| commit | 2dcc3a5c68b4bacbe96c1543cc20e5a3425889fb (patch) | |
| tree | 5e17b66c64aa3bb7d811241e1f37e1cebebdf3e7 /src/cpu/intel/socket_mFCPGA478 | |
| parent | 3aa9adba675b894fc7a1db41f9aea98eafeff88b (diff) | |
nb/intel/i945: Switch to POSTCAR_STAGE
Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel/socket_mFCPGA478')
| -rw-r--r-- | src/cpu/intel/socket_mFCPGA478/Makefile.inc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc index fb5902cea6..139b1bb624 100644 --- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc +++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc @@ -11,11 +11,7 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -ifneq ($(CONFIG_POSTCAR_STAGE),y) -cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc -else cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S postcar-y += ../car/p4-netburst/exit_car.S -endif romstage-y += ../car/romstage.c |