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authorRichard Smith <smithbone@gmail.com>2006-07-24 04:25:47 +0000
committerRichard Smith <smithbone@gmail.com>2006-07-24 04:25:47 +0000
commitcb8eab482ff09ec256456312ef2d6e7710123551 (patch)
tree7bc1297911194e564b967efba4a03c4dde5f7a13 /src/cpu/intel/socket_PGA370
parent4788effb045ae1f71d89c78a0b16a93d5ba79e89 (diff)
add framework for i440bx chipset
add support for NSC pc87351 SuperIO add Bitworks/IMS manboard config This is a very basic framework for the i440bx chipset and the Bitworks IMS board that uses it. Most things are structure only. Known issues: - SMbus reads to the RAM SPD come back all zero. - dump_spd_registers() is commented out since it breaks with the default setting of generic_dump_spd.c where it wants 2 memory controllers. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/socket_PGA370')
-rw-r--r--src/cpu/intel/socket_PGA370/Config.lb3
-rw-r--r--src/cpu/intel/socket_PGA370/chip.h4
-rw-r--r--src/cpu/intel/socket_PGA370/socket_PGA370.c7
3 files changed, 14 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_PGA370/Config.lb b/src/cpu/intel/socket_PGA370/Config.lb
new file mode 100644
index 0000000000..8db263b5a0
--- /dev/null
+++ b/src/cpu/intel/socket_PGA370/Config.lb
@@ -0,0 +1,3 @@
+config chip.h
+object socket_PGA370.o
+dir /cpu/intel/model_6xx
diff --git a/src/cpu/intel/socket_PGA370/chip.h b/src/cpu/intel/socket_PGA370/chip.h
new file mode 100644
index 0000000000..469b662dfb
--- /dev/null
+++ b/src/cpu/intel/socket_PGA370/chip.h
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_PGA370_ops;
+
+struct cpu_intel_socket_PGA370_config {
+};
diff --git a/src/cpu/intel/socket_PGA370/socket_PGA370.c b/src/cpu/intel/socket_PGA370/socket_PGA370.c
new file mode 100644
index 0000000000..690e69d0a9
--- /dev/null
+++ b/src/cpu/intel/socket_PGA370/socket_PGA370.c
@@ -0,0 +1,7 @@
+#include <device/device.h>
+#include "chip.h"
+
+
+struct chip_operations cpu_intel_socket_PGA370_ops = {
+ CHIP_NAME("socket PGA370")
+};