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authorShuo Liu <shuo.liu@intel.com>2024-04-26 17:35:05 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-05-02 17:43:42 +0000
commita0aff6e15988f918b926c4cd222537d2f5a3f878 (patch)
tree593424f7bba43c6b2361f305334c3ac8eac3f6e1 /src/cpu/intel/socket_LGA775
parentb25fa1cf9ee3ea51c4c183d2d7f3d79c0bf8d573 (diff)
soc/intel/xeon_sp: Add get_cxl_mode
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes. Add get_cxl_mode so that SoC codes do not need to get this configuration from VPD any more. TEST=Build and boot on intel/archercity CRB with no significant log differences Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu/intel/socket_LGA775')
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