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| author | Subrata Banik <subrata.banik@intel.com> | 2018-02-06 15:20:19 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-02-07 08:09:12 +0000 |
| commit | 828c39eb6ba4aa72ffb027a0fc70d8ec78a83d24 (patch) | |
| tree | 6acb3bc4c3d06e83a92650c33c84017633f48285 /src/cpu/intel/socket_FCBGA559 | |
| parent | 9076b7bd077810cb219ef2a58e999fad2b3e0b93 (diff) | |
soc/intel/common/block: Fix SATA chipset register definitions anomalies
SATA PCH configuration space registers bit mapping is different
for various SOCs hence common API between SPT-PCH and CNL-PCH causing
issue.
Add new Kconfig option to address this delta between different PCH.
Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/socket_FCBGA559')
0 files changed, 0 insertions, 0 deletions