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authorArthur Heymans <arthur@aheymans.xyz>2019-01-12 00:27:18 +0100
committerArthur Heymans <arthur@aheymans.xyz>2019-01-22 12:05:33 +0000
commitd30894b835eb466e6e46c64317edf96e5554b138 (patch)
treebb4aa95b7fdf7fa1908d9a7a7670111e1faa39b0 /src/cpu/intel/smm/gen1/smi.h
parent2c64a806eed13c6434c3354e9fbf8c8253c267c2 (diff)
cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's
Intel pineview has the same alternative SMRR MSR and IA32_FEATURE_CONTROL enable bit as core2 CPUs so properly check for that before enabling this feature. This also exposes a function to fetch whether alternative SMRR MSR's ought to be used. Change-Id: Iccaabfa95b8dc4366b8e7e2c2a526081d4af0efa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30868 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/smm/gen1/smi.h')
-rw-r--r--src/cpu/intel/smm/gen1/smi.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h
index f4cbbc3699..cc6811fd63 100644
--- a/src/cpu/intel/smm/gen1/smi.h
+++ b/src/cpu/intel/smm/gen1/smi.h
@@ -19,3 +19,5 @@ u32 northbridge_get_tseg_base(void);
u32 northbridge_get_tseg_size(void);
int cpu_get_apic_id_map(int *apic_id_map);
void northbridge_write_smram(u8 smram);
+
+bool cpu_has_alternative_smrr(void);