diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-22 16:33:24 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-30 10:21:43 +0100 |
| commit | 773485b8920145443da8b09712553c10c954fed1 (patch) | |
| tree | fff1c5eec6b6b7782da4d9d8c0afa3492bd583a8 /src/cpu/intel/slot_1 | |
| parent | 2b9814629b4b7d96340033fc38c5003e6a8db93e (diff) | |
intel CAR: Fix DCACHE_RAM_BASE for old sockets
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored
and was not correctly set on affected sockets and boards. It was still
referenced in romstage linker script. This was discovered by clang builds
failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed.
The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken
from intel/cpu/cache_as_ram.inc.
Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7887
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/cpu/intel/slot_1')
| -rw-r--r-- | src/cpu/intel/slot_1/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 57076d71cd..25bcbafe9b 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -30,6 +30,10 @@ config SLOT_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX +config DCACHE_RAM_BASE + hex + default 0xcf000 + config DCACHE_RAM_SIZE hex default 0x01000 |