diff options
| author | Joel Kitching <kitching@google.com> | 2018-11-16 14:33:07 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-17 13:19:47 +0000 |
| commit | dc8fd37966880d6e396e9168f030540f72cdafab (patch) | |
| tree | 7b3221f8a2e8c99801dbdcc946613b929e7ec184 /src/cpu/intel/slot_1/l2_cache.c | |
| parent | 60132a43a670276add0e3ea0e56511aabd2ce099 (diff) | |
tss/tcg-2.0: remove unnecessary break from marshaling code
BUG=None
TEST=None
Change-Id: I054e0799469bf39499666342a5c639b1f766cd85
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/29652
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/slot_1/l2_cache.c')
0 files changed, 0 insertions, 0 deletions