diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-08-08 21:27:32 +0200 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-13 19:28:24 +0000 |
| commit | b65845cb2b0009d1ed1e9b8550cbcd4c1d093c63 (patch) | |
| tree | caefdeffdd190b8bbd02fb6838a54995168fcb38 /src/cpu/intel/model_f3x/Makefile.inc | |
| parent | 5e0cd9fd4bba28ac3d07c17a0d1bee5cdeaf19f2 (diff) | |
vc/amd/fsp/cezanne,mendocino: add FSP CCX CPPC HOB GUID and struct
To generate a complete _CPC ACPI object, coreboot needs the minimal and
nominal core speed values which are specific to the CPU and not only the
CPU family. Since this is done by an undocumented mechanism, FSP has to
do this and puts the information we need into a HOB. This adds the HOB
GUID and the structure of the HOB data.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Ibf338c32de367a3fd57695873da1625338fa196d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66549
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_f3x/Makefile.inc')
0 files changed, 0 insertions, 0 deletions