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authorEric Biederman <ebiederm@xmission.com>2004-10-14 19:29:29 +0000
committerEric Biederman <ebiederm@xmission.com>2004-10-14 19:29:29 +0000
commitfcd5ace00b333ce31b11b02a2243dfbf39307f10 (patch)
treed686d752ccea9b185b0008c70d8523749b26e2dd /src/cpu/intel/model_f2x/model_f2x_init.c
parent98e619b1cefcb9871185f4cc3db85fa430dcdbce (diff)
- Add new cvs code to cvs
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_f2x/model_f2x_init.c')
-rw-r--r--src/cpu/intel/model_f2x/model_f2x_init.c66
1 files changed, 66 insertions, 0 deletions
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
new file mode 100644
index 0000000000..ecc454c974
--- /dev/null
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -0,0 +1,66 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/chip.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+
+/* 512KB cache */
+static uint32_t microcode_updates[] = {
+ /* WARNING - Intel has a new data structure that has variable length
+ * microcode update lengths. They are encoded in int 8 and 9. A
+ * dummy header of nulls must terminate the list.
+ */
+#include "microcode_m02f2203.h"
+#include "microcode_m02f2410.h"
+//#include "microcode_m02f2728.h"
+#include "microcode_m02f2734.h"
+#include "microcode_m02f2918.h"
+ /* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+
+static void model_f2x_init(device_t dev)
+{
+ /* Turn on caching if we haven't already */
+ x86_enable_cache();
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+
+ /* Update the microcode */
+ intel_update_microcode(microcode_updates);
+
+ /* Enable the local cpu apics */
+ setup_lapic();
+
+ /* Start up my cpu siblings */
+ intel_sibling_init(cpu);
+};
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_f1x_init,
+};
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, 0x0f22 },
+ { X86_VENDOR_INTEL, 0x0f24 },
+ { X86_VENDOR_INTEL, 0x0f27 },
+ { X86_VENDOR_INTEL, 0x0f29 },
+// { X86_VENDOR_INTEL, 0x0f25 }, /* I don't have a microcode update for this cpu */
+ { 0, 0 },
+};
+
+static struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};