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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-06-28 21:26:41 +0300 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2012-07-04 14:42:01 +0200 |
| commit | c7fb2ae67b0dc3c2c38f8ef630a3a72374440032 (patch) | |
| tree | 448b83999580196bbba058e61948825ad6c57004 /src/cpu/intel/model_6fx | |
| parent | 89f04a6d68cbb8faf9d90089cc76ee38bdf932ad (diff) | |
Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR
Default CPU_ADDR_BITS is 36.
For Atom (model_106cx) use 32. This model is known to
fail execution-in-place (XIP) with the default 36.
Pentium M should use 32, but doesn't even with this patch.
Some Xeon and CORE(2) models should use 38 or 40.
Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/639
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Diffstat (limited to 'src/cpu/intel/model_6fx')
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 61feb1d8b5..d8d25a0cb7 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -23,8 +23,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |