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authorStefan Reinauer <stepan@coresystems.de>2009-07-21 21:41:42 +0000
committerStefan Reinauer <stepan@openbios.org>2009-07-21 21:41:42 +0000
commit4da810bd53f3e47fe0c5de64b5cec0910237a022 (patch)
treea84537f4ed6e80281e7b68c9ff415551df41389a /src/cpu/intel/model_6fx
parentb657a3c9b726334aac89f1af16495eab3ebefc6b (diff)
add intel speedstep support and some PM fixes.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_6fx')
-rw-r--r--src/cpu/intel/model_6fx/model_6fx_init.c22
1 files changed, 18 insertions, 4 deletions
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index d716efbd48..37eb81fabf 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -126,9 +126,16 @@ static void enable_vmx(void)
#define PMG_IO_BASE_ADDR 0xe3
#define PMG_IO_CAPTURE_ADDR 0xe4
-#define PMB0_BASE 0x580
+/* MWAIT coordination I/O base address. This must match
+ * the \_PR_.CPU0 PM base address.
+ */
+#define PMB0_BASE 0x510
+
+/* PMB1: I/O port that triggers SMI once cores are in the same state.
+ * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
+ */
#define PMB1_BASE 0x800
-#define CST_RANGE 2
+#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
{
msr_t msr;
@@ -141,6 +148,10 @@ static void configure_c_states(void)
msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
msr.lo |= (1 << 3); // Dynamic L2
+ /* Number of supported C-States */
+ msr.lo &= ~7;
+ msr.lo |= HIGHEST_CLEVEL; // support at most C3
+
wrmsr(PMG_CST_CONFIG_CONTROL, msr);
/* Set Processor MWAIT IO BASE */
@@ -148,9 +159,9 @@ static void configure_c_states(void)
msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
wrmsr(PMG_IO_BASE_ADDR, msr);
- /* Set IO Capture Address */
+ /* Set C_LVL controls and IO Capture Address */
msr.hi = 0;
- msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16);
+ msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
wrmsr(PMG_IO_CAPTURE_ADDR, msr);
}
@@ -229,6 +240,9 @@ static void model_6fx_init(device_t cpu)
x86_setup_mtrrs(36);
x86_mtrr_check();
+ /* Setup Page Attribute Tables (PAT) */
+ // TODO set up PAT
+
#if CONFIG_USBDEBUG_DIRECT
set_ehci_debug(ehci_debug_addr);
#endif