diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-06-30 11:41:08 +0300 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2012-07-04 14:47:53 +0200 |
| commit | 5458b9d90a246833de55e0814f0c323a0cf6e471 (patch) | |
| tree | a4010f1ce9c9cdaa97cabc8ce1f97e0a09a199be /src/cpu/intel/model_6ex | |
| parent | ae7d6ef8b7ef5ca9c04d8d929332d18d563f723e (diff) | |
Intel cpus: Extend cache to cover complete Flash Device
CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set
in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup
would not cover the bottom 4 MB when ramstage is decompressed.
Verify CACHE_ROM_SIZE is power of two.
One may set CACHE_ROM_SIZE==0 to disable this cache.
Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1146
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Diffstat (limited to 'src/cpu/intel/model_6ex')
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index bdefb21b59..82a568ac1e 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -191,15 +191,17 @@ clear_mtrrs: movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable caching and Speculative Reads for the last 4MB. */ +#if CONFIG_CACHE_ROM_SIZE + /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif post_code(0x39) |