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authorKevin O'Connor <kevin@koconnor.net>2011-01-19 06:32:35 +0000
committerStefan Reinauer <stepan@openbios.org>2011-01-19 06:32:35 +0000
commit5bb9fd6e4dae32f86a07676228034d3828820037 (patch)
tree9933b8327f3af0ce6814d5402ce798a3720d273e /src/cpu/intel/model_6ex/microcode-1624-m206e839.h
parent4adc9eb60047e7dc3a7921793c489fff4fe3fc57 (diff)
Now that the VIA code is run above 1Meg (like other boards), it should
cache that range instead of the first 1Meg. This reduces boot time by about 1 second on epia-cn. This patch also adds a MTRRphysMaskValid bit definition. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_6ex/microcode-1624-m206e839.h')
0 files changed, 0 insertions, 0 deletions