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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-12 15:49:55 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-19 11:19:51 +0000 |
| commit | afc6c0ae12ddd26c05bcc2fa527c7a15d0bca0ad (patch) | |
| tree | db3d89c2712162e04577e2230984778c5ec9f869 /src/cpu/intel/model_6bx | |
| parent | 260e98fbe7c0aed5cbb1e4360fbaed32711e88d3 (diff) | |
mb/google/slippy: Correct memory-down SPD handling
MRC only uses the SPD data for the first index, and ignores the rest.
Moreover, index 1 corresponds to the second DIMM on the first channel,
which does not exist on ULT (only one DIMM per channel is supported).
Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge
code to retrieve the serial number from the correct SPD data block.
Tested on Google Wolf, both channels are still correctly detected.
Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/model_6bx')
0 files changed, 0 insertions, 0 deletions