diff options
| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-06 23:14:54 -0600 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-01-16 05:34:25 +0100 |
| commit | 2c38f50b4ad8850676a70427bf1e2e9e9aab82a4 (patch) | |
| tree | 68fe15f5e270e69ab9810b12fa2bf61d7ff71585 /src/cpu/intel/model_6bx | |
| parent | b4c39902edbba61827c60a75fe84e748e217b8be (diff) | |
cpu/intel: Make all Intel CPUs load microcode from CBFS
The sequence to inject microcode updates is virtually the same for all
Intel CPUs. The same function is used to inject the update in both CBFS
and hardcoded cases, and in both of these cases, the microcode resides in
the ROM. This should be a safe change across the board.
The function which loaded compiled-in microcode is also removed here in
order to prevent it from being used in the future.
The dummy terminators from microcode need to be removed if this change is
to work when generating microcode from several microcode_blob.c files, as
is the case for older socketed CPUs. Removal of dummy terminators is done
in a subsequent patch.
Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4495
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_6bx')
| -rw-r--r-- | src/cpu/intel/model_6bx/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_6bx/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_6bx/microcode_blob.c | 11 | ||||
| -rw-r--r-- | src/cpu/intel/model_6bx/model_6bx_init.c | 14 |
4 files changed, 15 insertions, 13 deletions
diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig index 10661d0d96..26b5995f68 100644 --- a/src/cpu/intel/model_6bx/Kconfig +++ b/src/cpu/intel/model_6bx/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_6BX bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc index 2d33f85d2f..5f1f8949ce 100644 --- a/src/cpu/intel/model_6bx/Makefile.inc +++ b/src/cpu/intel/model_6bx/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += model_6bx_init.c subdirs-y += ../../x86/name + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c new file mode 100644 index 0000000000..a6f9bc69c4 --- /dev/null +++ b/src/cpu/intel/model_6bx/microcode_blob.c @@ -0,0 +1,11 @@ +unsigned microcode_updates_6bx[] = { + #include "microcode-737-MU16b11c.h" + #include "microcode-738-MU16b11d.h" + #include "microcode-875-MU16b401.h" + #include "microcode-885-MU16b402.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index b7affd9dd5..e06665a2c2 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -32,18 +32,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-737-MU16b11c.h" - #include "microcode-738-MU16b11d.h" - #include "microcode-875-MU16b401.h" - #include "microcode-885-MU16b402.h" - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_6bx_init(device_t cpu) { char processor_name[49]; @@ -52,7 +40,7 @@ static void model_6bx_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); |