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authorNico Huber <nico.h@gmx.de>2022-08-05 14:50:06 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-08-17 19:09:05 +0000
commit5f7cfb388e6d267cea8c435643373d248d037470 (patch)
tree0481bd48c5b84c6efa3a1536c1d446009397d077 /src/cpu/intel/model_68x
parent077dc2eca2a1fbd105c04183ef8767f120f6fc12 (diff)
pciexp_device: Fix offset handling for extended capabilities
The PCIe spec explicitly states that the bottom-two bits of the next offset are reserved for future use and should be masked. We can also change the loop condition to avoid wrong offsets below 0x100 (exten- ded capabilities always reside in the extended config space). The whole patch series was tested on Google Samus and keeps the L1ss configuration of the WiFi device in tact. Change-Id: I0b622a0ce0a4a1127d266226ade0ec1e66e9fb79 Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66459 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_68x')
0 files changed, 0 insertions, 0 deletions