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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-18 19:03:29 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-20 21:21:36 +0100 |
| commit | c13d65c29b6219d4b765f40e661548eb389524b5 (patch) | |
| tree | 097ad2b0071faf8522cb4d35d6a453d6bca1f18d /src/cpu/intel/model_206ax | |
| parent | 51e238d3b4ace91bab9b6ae2a1c69409a0144205 (diff) | |
intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT
Compiled romstage is over 64kiB and exceeded XIP_ROM_SIZE,
so it was not entirely set WRPROT cacheable.
Reduces first boot raminit (including training) time by 400ms.
Change-Id: I5c4cbf581fc845150f207087c1527338ca364f60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17488
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/model_206ax')
| -rw-r--r-- | src/cpu/intel/model_206ax/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 8f062e53fa..b954b79c61 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -25,6 +25,10 @@ config BOOTBLOCK_CPU_INIT string default "cpu/intel/model_206ax/bootblock.c" +config XIP_ROM_SIZE + hex + default 0x20000 if USE_NATIVE_RAMINIT + config SMM_TSEG_SIZE hex default 0x800000 |