From c13d65c29b6219d4b765f40e661548eb389524b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 18 Nov 2016 19:03:29 +0200 Subject: intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Compiled romstage is over 64kiB and exceeded XIP_ROM_SIZE, so it was not entirely set WRPROT cacheable. Reduces first boot raminit (including training) time by 400ms. Change-Id: I5c4cbf581fc845150f207087c1527338ca364f60 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17488 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph Reviewed-by: Aaron Durbin --- src/cpu/intel/model_206ax/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/cpu/intel/model_206ax') diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 8f062e53fa..b954b79c61 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -25,6 +25,10 @@ config BOOTBLOCK_CPU_INIT string default "cpu/intel/model_206ax/bootblock.c" +config XIP_ROM_SIZE + hex + default 0x20000 if USE_NATIVE_RAMINIT + config SMM_TSEG_SIZE hex default 0x800000 -- cgit v1.2.3