intel/nehalem,sandybridge: Move stage_cache support function

Let garbage-collection take care of stage_cache_external_region()
if it is no needed and move implementation to a suitable file already
building for needed stages.

Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE and
(unused) aliasing of CONFIG_IED_REGION_SIZE as IED_SIZE.

Change-Id: Idf00ba3180d8c3bc974dd3c5ca5f98a6c08bf34d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34672
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 28 deletions

diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c
deleted file mode 100644
index 26dc5e03f9..0000000000
--- a/src/cpu/intel/model_206ax/stage_cache.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <stage_cache.h>
-#include "model_206ax.h"
-
-void stage_cache_external_region(void **base, size_t *size)
-{
-	/*
-	 * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
-	 * The top of RAM is defined to be the TSEG base address.
-	 */
-	*size = RESERVED_SMM_SIZE;
-	*base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET);
-}