diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2018-02-05 19:08:03 +0100 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 09:30:21 +0000 |
commit | 67031a565b3179fa5a28282fc2e24b47d16003e8 (patch) | |
tree | d56eaf320fcdc2b2940a24d77c20077fb970951c /src/cpu/intel/model_206ax/stage_cache.c | |
parent | 64f0bcb6b0c4ee0fb55e6e600a48a1c61d2e97ef (diff) |
cpu/intel/sandybridge: Put stage cache into TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
The code is mostly copied from src/cpu/intel/haswell.
TESTED on Thinkpad X220: on a cold boot the stage cache gets created
and on S3 the cached ramstage gets properly used.
Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/model_206ax/stage_cache.c')
-rw-r--r-- | src/cpu/intel/model_206ax/stage_cache.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c new file mode 100644 index 0000000000..26dc5e03f9 --- /dev/null +++ b/src/cpu/intel/model_206ax/stage_cache.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <stage_cache.h> +#include "model_206ax.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = RESERVED_SMM_SIZE; + *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); +} |