diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-12-18 22:25:07 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-24 01:18:56 +0000 |
| commit | fa5ed059eb6fef1aa1681fbc7b38052b2028c1ac (patch) | |
| tree | 6dc67b2015e4f45b3cf842bda771d23ffd0c0848 /src/cpu/intel/model_2065x | |
| parent | e2531ffaa87be5c26005ff986db8492a03f809e3 (diff) | |
nb/intel/ironlake: Fix some quickpath init magic
Correct some Quickpath initialisation steps according to findings from
two different Intel reference code binaries as well as MCHBAR register
dump comparisons between vendor firmware and coreboot.
The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources.
Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init
now completes successfully instead of causing hangs before raminit.
Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still
reaches payload (e.g. TianoCore).
Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/intel/model_2065x')
| -rw-r--r-- | src/cpu/intel/model_2065x/model_2065x.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 9c8b18039f..251fd75b50 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -20,6 +20,7 @@ #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MSR_TURBO_POWER_CURRENT_LIMIT 0x1ac #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_POWER_CTL 0x1fc |