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authorElyes HAOUAS <ehaouas@noos.fr>2019-05-26 13:25:30 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-06-21 08:55:44 +0000
commita6a396ddb6f866c5a675dff5c1aa0b4cbaf44039 (patch)
tree64f29e2f33a26eff273488f68fc12cf9b5cc086b /src/cpu/intel/model_2065x
parent3286848a7a013b4d4effc4e50b4b7b552236cf73 (diff)
cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35
Regarding 64 and IA-32 Architectures Software Developer’s Manual, the register name of the msr at 0x35 is MSR_CORE_THREAD_COUNT. Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33015 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_2065x')
-rw-r--r--src/cpu/intel/model_2065x/model_2065x.h2
-rw-r--r--src/cpu/intel/model_2065x/model_2065x_init.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index e7ba2a771b..eab2dd5c50 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -20,7 +20,7 @@
/* Nehalem bus clock is fixed at 133MHz */
#define NEHALEM_BCLK 133
-#define CORE_THREAD_COUNT_MSR 0x35
+#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index d8de7c055f..289d4471e6 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -287,7 +287,7 @@ static int get_cpu_count(void)
int num_threads;
int num_cores;
- msr = rdmsr(CORE_THREAD_COUNT_MSR);
+ msr = rdmsr(MSR_CORE_THREAD_COUNT);
num_threads = (msr.lo >> 0) & 0xffff;
num_cores = (msr.lo >> 16) & 0xffff;
printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",