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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-12-08 13:21:49 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-01 08:45:15 +0000 |
| commit | 129ed0a26470ab8b0bbecd77700c7016d14ef95d (patch) | |
| tree | d936523fa60c06e22c1780beb7b85a6e00532d18 /src/cpu/intel/model_2065x/chip.h | |
| parent | 98cc7830e77d9395034a9346ce890b69c23f00e8 (diff) | |
soc/intel/xeon_sp: Use native CAR teardown
This cleans up the postcar frame setup, which now gets used instead of
just going with TempRamExit MTRR's.
Note that ramstage CPU init sets up different final MTRRs anyway.
TESTED on ocp/deltalake and ocp/tiogapass.
Change-Id: I756c2d479fef859a460696300422f08013a300f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_2065x/chip.h')
0 files changed, 0 insertions, 0 deletions