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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-04-24 12:29:44 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-25 15:56:28 +0000 |
| commit | 74f9fe6e58f949001a34866505cecca16aa0de03 (patch) | |
| tree | a46a7d5f92669425a05f8394918c1b6be1e74c91 /src/cpu/intel/model_2065x/Kconfig | |
| parent | 5417c84f7d525d1db8f4abbf3ef4da527dd52cd6 (diff) | |
cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE
CPU's featuring a non eviction mode cache the whole ROM.
Therefore XIP stages don't need to follow some alignment constraints.
Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_2065x/Kconfig')
| -rw-r--r-- | src/cpu/intel/model_2065x/Kconfig | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 9481917ff8..ba2b7de74d 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON + select NO_FIXED_XIP_ROM_SIZE config BOOTBLOCK_CPU_INIT string @@ -28,8 +29,4 @@ config SMM_TSEG_SIZE hex default 0x800000 -config XIP_ROM_SIZE - hex - default 0x20000 - endif |