diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-15 18:26:18 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-16 04:14:27 +0100 |
| commit | cdc50480c414df3b5f438f7f26a73df597e544ae (patch) | |
| tree | 2b373cab7ce4679a534420579ae2790302166ce2 /src/cpu/intel/model_106cx | |
| parent | 26eeb0f8ad554b1fa08d58080da8ce2d22081c1c (diff) | |
cpu/intel: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build and run on Galileo Gen2
Change-Id: I74f25da5c53bd518189ce86817d6e3385b29c3b4
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18850
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/model_106cx')
| -rw-r--r-- | src/cpu/intel/model_106cx/model_106cx_init.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index d9ce736787..b07fd0b79b 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -34,7 +34,8 @@ static void configure_c_states(void) msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // Lock configuration - msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT + msr.lo |= (1 << 10); // redirect IO-based CState transition requests to + // MWAIT msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 // TODO Do we want Deep C4 and Dynamic L2 shrinking? @@ -43,13 +44,15 @@ static void configure_c_states(void) /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; // TODO Do we want PM1_BASE? Needs SMM? - //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); + //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) + // << 16); msr.lo = ((PMB0_BASE + 4) & 0xffff); wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* set C_LVL controls */ msr.hi = 0; - msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted + // -2 because LVL0+1 aren't counted + msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } |