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authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-09-26 10:26:49 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-10-01 15:10:16 +0000
commit6e079dc120a4aa95a25cfe536d4b1acd178918fd (patch)
treec8b1d76e5dd361964389c0f628b162102e72add1 /src/cpu/intel/model_106cx
parent5adbc767f66224e617b6c8204a868542b8010999 (diff)
cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/model_106cx')
-rw-r--r--src/cpu/intel/model_106cx/Makefile.inc1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 6701e6fc18..6d8414ec16 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -1,6 +1,5 @@
ramstage-y += model_106cx_init.c
subdirs-y += ../../x86/name
-subdirs-y += ../common
subdirs-y += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c