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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-12-16 05:46:16 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-17 18:13:38 +0000 |
| commit | 9612a3c32a95791c1084ade5ae89e9147b2c2b7b (patch) | |
| tree | 7094c29ddd82729151c048b45c8f6ca022114fe6 /src/cpu/intel/microcode/Kconfig | |
| parent | 555efe47922c8b347ad7cd2c9759740e3e228164 (diff) | |
cpu/intel: Remove ROMCC header guards and code
Intel's platforms use a GCC compiled bootblock.
Change-Id: I779d7115fee75df9356873e9cc66d43280821812
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/cpu/intel/microcode/Kconfig')
| -rw-r--r-- | src/cpu/intel/microcode/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 73afe0bb45..238aad745d 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -1,7 +1,7 @@ config MICROCODE_UPDATE_PRE_RAM bool depends on SUPPORT_CPU_UCODE_IN_CBFS - default y if !ROMCC_BOOTBLOCK + default y help Select this option if you want to update the microcode during the cache as ram setup. |