From 9612a3c32a95791c1084ade5ae89e9147b2c2b7b Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Mon, 16 Dec 2019 05:46:16 +0100
Subject: cpu/intel: Remove ROMCC header guards and code
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Intel's platforms use a GCC compiled bootblock.

Change-Id: I779d7115fee75df9356873e9cc66d43280821812
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
 src/cpu/intel/microcode/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/cpu/intel/microcode/Kconfig')

diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig
index 73afe0bb45..238aad745d 100644
--- a/src/cpu/intel/microcode/Kconfig
+++ b/src/cpu/intel/microcode/Kconfig
@@ -1,7 +1,7 @@
 config MICROCODE_UPDATE_PRE_RAM
 	bool
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
-	default y if !ROMCC_BOOTBLOCK
+	default y
 	help
 	  Select this option if you want to update the microcode
 	  during the cache as ram setup.
-- 
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