diff options
| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2021-10-22 23:41:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-26 15:37:56 +0000 |
| commit | 8023eabde1dd3e830ee9a34437591070e60a1a75 (patch) | |
| tree | 1a0736846ee0b2a6e877d253cf51541db6e685e2 /src/cpu/intel/haswell | |
| parent | 3a79633920850cb1d44f515a9cfe8372c6c01341 (diff) | |
cpu/amd,intel/*/Makefile: don't add cpu/x86/cache
Some CPUs don't use the ramstage-only x86_enable_cache helper function
to call enable_cache with some added port 0x80 and console output.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ia44c7b150cd12d76e463903966f67d86750cbdd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index a46effe874..ec0ceea06d 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -16,7 +16,6 @@ bootblock-y += bootblock.c postcar-y += ../car/non-evict/exit_car.S subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache subdirs-y += ../microcode subdirs-y += ../turbo |