diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-08 12:13:15 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-11 18:52:09 +0100 |
| commit | 39915bc290066174b8b933829b7d192b86bb8e6f (patch) | |
| tree | fb283a5f20bfa68e470532f4823640278662de1f /src/cpu/intel/haswell | |
| parent | a4ffe9dda0eb50eb698fef303f426408338fa0ff (diff) | |
intel cache-as-ram: Unify stack setup
No need to have %ebx reserved here.
Change-Id: I9fe9292ddc610079b876019a71c69af5b1bcf2a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17357
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 276b9c3a63..f0d49390ba 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -177,7 +177,7 @@ before_romstage: /* Save return value from romstage_main. It contains the stack to use * after cache-as-ram is torn down. It also contains the information * for setting up MTRRs. */ - movl %eax, %ebx + movl %eax, %esp post_code(0x30) @@ -225,9 +225,6 @@ before_romstage: post_code(0x38) - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - /* Get number of MTRRs. */ popl %ebx movl $MTRR_PHYS_BASE(0), %ecx |