From 39915bc290066174b8b933829b7d192b86bb8e6f Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 8 Nov 2016 12:13:15 +0200 Subject: intel cache-as-ram: Unify stack setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No need to have %ebx reserved here. Change-Id: I9fe9292ddc610079b876019a71c69af5b1bcf2a2 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17357 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/haswell/cache_as_ram.inc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/cpu/intel/haswell') diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 276b9c3a63..f0d49390ba 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -177,7 +177,7 @@ before_romstage: /* Save return value from romstage_main. It contains the stack to use * after cache-as-ram is torn down. It also contains the information * for setting up MTRRs. */ - movl %eax, %ebx + movl %eax, %esp post_code(0x30) @@ -225,9 +225,6 @@ before_romstage: post_code(0x38) - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - /* Get number of MTRRs. */ popl %ebx movl $MTRR_PHYS_BASE(0), %ecx -- cgit v1.2.3