diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-02-08 22:18:04 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-18 20:50:45 +0100 |
| commit | 7492ec1ca62efee1f244d8306b03ed3d74ac2e53 (patch) | |
| tree | 9748ad946aae129e78c7b7b43b9f221ce63510e7 /src/cpu/intel/haswell/haswell.h | |
| parent | 2ad1dbaf2a2dfe373ff89927202acc01e36c7cd4 (diff) | |
haswell: add romstage_after_car() function
There are changes coming to perform more complex tasks after cache-as-ram
has been torn down but before ramstage is loaded. Therefore, add the
romstage_after_car() function to call after cache-as-ram is torn down.
Its responsibility is for loading the ramstage and any other complex
tasks. For example, the saving of OS-controlled memory in the resume
path has now been moved into C instead of assembly.
Change-Id: Ie0c229cf83a9271c8995b31c534c8e5a696b164e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2757
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/haswell.h')
| -rw-r--r-- | src/cpu/intel/haswell/haswell.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 7a55ef7dac..733ddd3039 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -129,6 +129,9 @@ void romstage_common(const struct romstage_params *params); * ... */ void * __attribute__((regparm(0))) romstage_main(unsigned long bist); +/* romstage_after_car() is the C function called after cache-as-ram has + * been torn down. It is responsible for loading the ramstage. */ +void romstage_after_car(void); #endif #ifdef __SMM__ |