diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-02-07 00:03:33 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-18 20:49:46 +0100 |
| commit | 38d9423dbe300514e1ba7224a962650980a96217 (patch) | |
| tree | 6852430fd98517b90cc91188b22c52cb20b9c66e /src/cpu/intel/haswell/haswell.h | |
| parent | a267161362f23b94f2e7677a8ea55f729578a049 (diff) | |
haswell: romstage: pass stack pointer and MTRRs
Instead of hard coding the policy for the stack and MTRR values after
the cache-as-ram is torn down, allow for the C code to pass those
policies back to the cache-as-ram assembly file. That way, ramstage
relocation can use a different stack as well as different MTRR policies.
Change-Id: Ied024d933f96a12ed0703c51c506586f4b50bd14
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2755
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/haswell.h')
| -rw-r--r-- | src/cpu/intel/haswell/haswell.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 3ced0c08db..7a55ef7dac 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -113,6 +113,22 @@ struct romstage_params { }; void mainboard_romstage_entry(unsigned long bist); void romstage_common(const struct romstage_params *params); +/* romstage_main is called from the cache-as-ram assembly file. The return + * value is the stack value to be used for romstage once cache-as-ram is + * torn down. The following values are pushed onto the stack to setup the + * MTRRs: + * +0: Number of MTRRs + * +4: MTTR base 0 31:0 + * +8: MTTR base 0 63:32 + * +12: MTTR mask 0 31:0 + * +16: MTTR mask 0 63:32 + * +20: MTTR base 1 31:0 + * +24: MTTR base 1 63:32 + * +28: MTTR mask 1 31:0 + * +32: MTTR mask 1 63:32 + * ... + */ +void * __attribute__((regparm(0))) romstage_main(unsigned long bist); #endif #ifdef __SMM__ |