diff options
author | Aaron Durbin <adurbin@chromium.org> | 2013-07-03 16:21:28 -0500 |
---|---|---|
committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-07 03:51:52 +0100 |
commit | 16cbf8983c2481a31357f25c44a09b670edcf870 (patch) | |
tree | df7e3ee1161e3ceab4647a05ca34b9facd1a4849 /src/cpu/intel/haswell/haswell.h | |
parent | 01ab2d14be086bd6fda82eaad000a34e6abb9047 (diff) |
haswell: VR controller configuration
Configure the VR controller. This enables the PSIx levels
as well as C-state ramping. PSIx thresholds are:
- PSI3: 1A.
- PSI2: 5A.
- PSI1: 15A.
Before:
0x601 0x0000000000000100
0x603 0x0036000000262626
0x636 0x000000000000006f
After:
0x601 0x4010140f00000100
0x603 0x0036000000262626
0x636 0x000000000000006f
Change-Id: I6958845ac4164ebd0f1bb2d6d9be55ba63ed9344
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60931
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: http://review.coreboot.org/4338
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/intel/haswell/haswell.h')
-rw-r--r-- | src/cpu/intel/haswell/haswell.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 387521722a..e8c224944a 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -83,9 +83,11 @@ #define PKG_POWER_LIMIT_TIME_MASK 0x7f #define MSR_VR_CURRENT_CONFIG 0x601 +#define MSR_VR_MISC_CONFIG 0x603 #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_SKU 0x614 #define MSR_DDR_RAPL_LIMIT 0x618 +#define MSR_VR_MISC_CONFIG2 0x636 #define MSR_PP0_POWER_LIMIT 0x638 #define MSR_PP1_POWER_LIMIT 0x640 |