cpu/intel: Use CPU_INTEL_COMMON_TIMEBASE

Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 0 insertions, 8 deletions

diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index d46a422e4a..7661a4e2d8 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -1,27 +1,19 @@
 ramstage-y += haswell_init.c
-ramstage-y += tsc_freq.c
 romstage-y += romstage.c
-romstage-y += tsc_freq.c
 romstage-y += ../car/romstage.c
 
-postcar-y += tsc_freq.c
-
 ramstage-y += acpi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
 
 smm-y += finalize.c
-smm-y += tsc_freq.c
 
 bootblock-y += ../car/non-evict/cache_as_ram.S
 bootblock-y += ../car/bootblock.c
 bootblock-y += ../../x86/early_reset.S
 bootblock-y += bootblock.c
-bootblock-y += tsc_freq.c
 
 postcar-y += ../car/non-evict/exit_car.S
 
-verstage-y += tsc_freq.c
-
 subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic