From c00e2fb9966a9c4bd30944a198ad036ee81a2b0d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 11 Feb 2019 11:36:17 +0200 Subject: cpu/intel: Use CPU_INTEL_COMMON_TIMEBASE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31342 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/intel/haswell/Makefile.inc | 8 -------- 1 file changed, 8 deletions(-) (limited to 'src/cpu/intel/haswell/Makefile.inc') diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index d46a422e4a..7661a4e2d8 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,27 +1,19 @@ ramstage-y += haswell_init.c -ramstage-y += tsc_freq.c romstage-y += romstage.c -romstage-y += tsc_freq.c romstage-y += ../car/romstage.c -postcar-y += tsc_freq.c - ramstage-y += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c smm-y += finalize.c -smm-y += tsc_freq.c bootblock-y += ../car/non-evict/cache_as_ram.S bootblock-y += ../car/bootblock.c bootblock-y += ../../x86/early_reset.S bootblock-y += bootblock.c -bootblock-y += tsc_freq.c postcar-y += ../car/non-evict/exit_car.S -verstage-y += tsc_freq.c - subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic -- cgit v1.2.3