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| author | Aaron Durbin <adurbin@chromium.org> | 2013-04-29 16:57:10 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-05-01 07:14:36 +0200 |
| commit | c46cc6f149c42653344d6e9f3656a4212fc46cef (patch) | |
| tree | 785ff1c5861ac336546f6c1ba98e5997edf0e222 /src/cpu/intel/haswell/Kconfig | |
| parent | a421791db815fb2e2da9b1ce4bec78c97665b62f (diff) | |
haswell: 24MHz monotonic time implementation
Haswell ULT devices have a 24MHz package-level counter. Use
this counter to provide a timer_monotonic_get() implementation.
Change-Id: Ic79843fcbfbbb6462ee5ebd12b39502307750dbb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3153
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/Kconfig')
| -rw-r--r-- | src/cpu/intel/haswell/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 5f27d4c7e1..13861f9185 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -54,4 +54,11 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE the system will reset otherwise the ramstage will be reloaded from cbfs. +config MONOTONIC_TIMER_MSR + def_bool n + depends on INTEL_LYNXPOINT_LP + select HAVE_MONOTONIC_TIMER + help + Provide a monotonic timer using the 24MHz MSR counter. + endif |