diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-05-10 00:51:43 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2013-05-16 01:30:25 +0200 |
| commit | 5b54d353aa89685c1cde0d6254a9899cf327a712 (patch) | |
| tree | af56367788f69a4ab61040ae16b15806b2b1b0dd /src/cpu/intel/haswell/Kconfig | |
| parent | 2ad6bd23a7ebcaf593f717db9c356284237ed639 (diff) | |
haswell: enable cache-as-ram migration
The haswell code allows for vboot ramstage verification.
However, that code path relies on accessing global cache-as-ram
variables after cache-as-ram is torn down. In order to avoid
that situation enable cache-as-ram migration.
cbmemc_reinit() no longer needs to be called from romstage
because it is invoked automatically by the cache-as-ram
migration infrastructure.
Change-Id: I08998dca579c167699030e1e24ea0af8802c0758
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/haswell/Kconfig')
| -rw-r--r-- | src/cpu/intel/haswell/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 152059fcbe..4c61b2d1da 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CAR_MIGRATION config BOOTBLOCK_CPU_INIT string |