diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-15 17:16:59 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-16 04:13:06 +0100 |
| commit | 7b5f12b9b2695359b6ccb4d62bdb868166c7f8d1 (patch) | |
| tree | 6b04150aa316965fd472b3dc127c374df6b34469 /src/cpu/intel/fsp_model_406dx | |
| parent | dfc8a560d7fec715a652f428dc3cab3e0a92c680 (diff) | |
cpu/intel: Indent with tabs
Fix the following error and warning detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
WARNING: please, no space before tabs
TEST=Build and run on Galileo Gen2
Change-Id: I5bcd82561ef5856e99055d46528dcf3a283d2310
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/fsp_model_406dx')
| -rw-r--r-- | src/cpu/intel/fsp_model_406dx/bootblock.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/fsp_model_406dx/model_406dx.h | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 99a27a74af..95eb5090d5 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -61,7 +61,7 @@ static void enable_rom_caching(void) disable_cache(); set_var_mtrr(1, 0xffffffff - CACHE_ROM_SIZE + 1, - CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); + CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); enable_cache(); /* Enable Variable MTRRs */ diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 805fef11ef..87daeac0ea 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -31,7 +31,7 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 +#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 @@ -39,7 +39,7 @@ #define ENERGY_POLICY_POWERSAVE 15 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 +#define IA32_MC0_STATUS 0x401 #define MSR_NO_EVICT_MODE 0x2e0 #define MSR_PIC_MSG_CONTROL 0x2e |