diff options
| author | Martin Roth <martinroth@google.com> | 2015-10-11 10:36:26 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-10-14 22:49:03 +0000 |
| commit | 58562405c8c416a415652516b8af31b204b4ff0d (patch) | |
| tree | 3311f3f5feceea80a048337f0485fc9c956ee5ac /src/cpu/intel/fsp_model_406dx/chip.h | |
| parent | 83e4c5613eecc5283d9a66997dc90e26384f9284 (diff) | |
Revert "Remove FSP Rangeley SOC and mohonpeak board support"
This chip is still being used and should not have been deleted. It's
a current intel chip, and doesn't even require an ME binary.
This reverts commit 959478a763c16688d43752adbae2c76e7764da45.
Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/fsp_model_406dx/chip.h')
| -rw-r--r-- | src/cpu/intel/fsp_model_406dx/chip.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/cpu/intel/fsp_model_406dx/chip.h b/src/cpu/intel/fsp_model_406dx/chip.h new file mode 100644 index 0000000000..a59e4031d3 --- /dev/null +++ b/src/cpu/intel/fsp_model_406dx/chip.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef CPU_FSP_MODEL406DX_CHIP_H +#define CPU_FSP_MODEL406DX_CHIP_H + +/* Magic value used to locate this chip in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + +struct cpu_intel_fsp_model_406dx_config { + int c1_battery; /* ACPI C1 on Battery Power */ + int c2_battery; /* ACPI C2 on Battery Power */ + int c3_battery; /* ACPI C3 on Battery Power */ + + int c1_acpower; /* ACPI C1 on AC Power */ + int c2_acpower; /* ACPI C2 on AC Power */ + int c3_acpower; /* ACPI C3 on AC Power */ +}; + +#endif /* CPU_FSP_MODEL406DX_CHIP_H */ |