diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-15 17:40:50 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-16 04:13:24 +0100 |
| commit | 9d62e7e75e43d6737df9d0ab5603446d7f5e408d (patch) | |
| tree | 318963e23b89ca65cc05502774d0af1e831af578 /src/cpu/intel/fsp_model_406dx/bootblock.c | |
| parent | 7b5f12b9b2695359b6ccb4d62bdb868166c7f8d1 (diff) | |
cpu/intel: Fix the spacing issues
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: need consistent spacing around '-' (ctx:WxV)
ERROR: spaces required around that '>' (ctx:VxV)
ERROR: need consistent spacing around '>>' (ctx:WxV)
ERROR: need consistent spacing around '<<' (ctx:VxW)
ERROR: spaces required around that '||' (ctx:VxV)
ERROR: "foo * bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
WARNING: space prohibited between function name and open parenthesis '('
WARNING: storage class should be at the beginning of the declaration
TEST=Build and run on Galileo Gen2
Change-Id: I6602fbc8602171ab6c2f3b6c204558ad2c811179
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18847
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/fsp_model_406dx/bootblock.c')
| -rw-r--r-- | src/cpu/intel/fsp_model_406dx/bootblock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 95eb5090d5..ee4cfac2de 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -36,8 +36,8 @@ static void check_for_warm_reset(void) * Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set. * If either is true, then this is a warm reset so execute a Hard Reset */ - if ( (inb(0xcf9) == 0x04) || - (pci_io_read_config32(SOC_LPC_DEV, RCBA) & RCBA_ENABLE) ) { + if ((inb(0xcf9) == 0x04) || + (pci_io_read_config32(SOC_LPC_DEV, RCBA) & RCBA_ENABLE)) { outb(0x00, 0xcf9); outb(0x06, 0xcf9); } |