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authorMartin Roth <martinroth@google.com>2015-11-05 09:00:20 -0700
committerMartin Roth <martinroth@google.com>2015-12-06 18:36:12 +0100
commitea7b6366075ef9f3eac5c6b75b58c153f8875581 (patch)
treecf1908fd7d255eccc4d3ee6034e6d3538fb4d7de /src/cpu/intel/fsp_model_406dx/Makefile.inc
parentc4fa3fdd3ea3f8e05cbbc881d45d1fb1927b525d (diff)
fsp_model_406dx: use external microcode .h files for rangeley
The microcode for the Rangeley chip is supplied as .h files in the Rangeley FSP POSTGOLD4 package. When the rangeley microcode gets put into the blobs directory, this can be reverted and the binary file put into the makefile. Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/fsp_model_406dx/Makefile.inc')
-rw-r--r--src/cpu/intel/fsp_model_406dx/Makefile.inc3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 91c7d96aa4..3e293480c2 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -23,6 +23,3 @@ cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
endif
CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-# We don't have microcode for this CPU
-# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
-# cpu_microcode_bins += ???