diff options
| author | Martin Roth <martinroth@google.com> | 2015-10-11 10:36:26 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-10-14 22:49:03 +0000 |
| commit | 58562405c8c416a415652516b8af31b204b4ff0d (patch) | |
| tree | 3311f3f5feceea80a048337f0485fc9c956ee5ac /src/cpu/intel/fsp_model_406dx/Kconfig | |
| parent | 83e4c5613eecc5283d9a66997dc90e26384f9284 (diff) | |
Revert "Remove FSP Rangeley SOC and mohonpeak board support"
This chip is still being used and should not have been deleted. It's
a current intel chip, and doesn't even require an ME binary.
This reverts commit 959478a763c16688d43752adbae2c76e7764da45.
Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/fsp_model_406dx/Kconfig')
| -rw-r--r-- | src/cpu/intel/fsp_model_406dx/Kconfig | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig new file mode 100644 index 0000000000..163040970f --- /dev/null +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -0,0 +1,65 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +config CPU_INTEL_FSP_MODEL_406DX + bool + +if CPU_INTEL_FSP_MODEL_406DX + +config CPU_SPECIFIC_OPTIONS + def_bool y + select PLATFORM_USES_FSP1_0 + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select SMP + select SSE2 + select UDELAY_LAPIC + select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN + select PARALLEL_CPU_INIT + select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER + +choice + prompt "Rangeley CPU Stepping" + default FSP_MODEL_406DX_B0 + +config FSP_MODEL_406DX_A1 + bool "A1" + +config FSP_MODEL_406DX_B0 + bool "B0" + +endchoice + +config BOOTBLOCK_CPU_INIT + string + default "cpu/intel/fsp_model_406dx/bootblock.c" + +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + +config CPU_MICROCODE_CBFS_LOC + hex + depends on SUPPORT_CPU_UCODE_IN_CBFS + default 0xfff60040 + +endif #CPU_INTEL_FSP_MODEL_406DX |