diff options
| author | Martin Roth <martinroth@google.com> | 2015-10-11 10:37:02 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-10-22 21:51:01 +0200 |
| commit | bf6b83abe06ff53033e7cd74134972de6791cf26 (patch) | |
| tree | 39d542ba472cd4398a030989e824e661a8751d49 /src/cpu/intel/fsp_model_206ax/chip.h | |
| parent | a4ffe8aa4981130b240eee5ed22c5bbfa1c7598b (diff) | |
Revert "Remove sandybridge and ivybridge FSP code path"
Please don't remove chipsets and mainboards without discussion and input
from the owners. Someone was asking about cougar canyon 2 just a couple
of weeks ago - there's obviously still interest.
This reverts commit fb50124d22014742b6990a95df87a7a828e891b6.
Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/12128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/fsp_model_206ax/chip.h')
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/chip.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/chip.h b/src/cpu/intel/fsp_model_206ax/chip.h new file mode 100644 index 0000000000..759a74cdde --- /dev/null +++ b/src/cpu/intel/fsp_model_206ax/chip.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Magic value used to locate this chip in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + +struct cpu_intel_fsp_model_206ax_config { + u8 disable_acpi; /* Do not generate CPU ACPI tables */ + + int c1_battery; /* ACPI C1 on Battery Power */ + int c2_battery; /* ACPI C2 on Battery Power */ + int c3_battery; /* ACPI C3 on Battery Power */ + + int c1_acpower; /* ACPI C1 on AC Power */ + int c2_acpower; /* ACPI C2 on AC Power */ + int c3_acpower; /* ACPI C3 on AC Power */ + + int tcc_offset; /* TCC Activation Offset */ +}; |