diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-12-15 15:57:33 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-20 22:18:05 +0000 |
| commit | f9aed6578565593ff2b5d9e90f8e6e80e5d9831d (patch) | |
| tree | 248a89e4ed74073abb525a543e828722f1fbdac7 /src/cpu/intel/common/common.h | |
| parent | c5ad267a372f376cee90c1b8a0d9b8a96316ddb8 (diff) | |
cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx()
Newer CPUs/SoCs need to configure other features via the
IA32_FEATURE_CONTROL msr, such as SGX, which cannot be done if the
msr is already locked. Create separate functions for setting the
vmx flag and lock bit, and rename existing function to indicate that
the lock bit will be set in addition to vmx flag (per Kconfig).
This will allow Skylake/Kabylake (and others?) to use the common
VMX code without breaking SGX, while ensuring no change in functionality
to existing platforms which current set both together.
Test: build/boot each affected platform, ensure no change in functionality
Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30229
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/common/common.h')
| -rw-r--r-- | src/cpu/intel/common/common.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index 81c9f16d19..b9ac0566c6 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -15,7 +15,9 @@ #ifndef _CPU_INTEL_COMMON_H #define _CPU_INTEL_COMMON_H -void set_vmx(void); +void set_vmx_and_lock(void); +void set_feature_ctrl_vmx(void); +void set_feature_ctrl_lock(void); /* * Init CPPC block with MSRs for Intel Enhanced Speed Step Technology. |