Tobias Diedrich wrote:

> Definitively a iasl problem, it can't even disassemble it's own
> output back to something equivalent to the input file.
> It seems to be generating Bytecode for the Add where it shouldn't.

Here is a solution using the SSDT.

Unfortunately iasl does not resolve simple arithmetic at compile
time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the
Processor statement.
This patch instead dynamically generates the processor statement.
I can't use the speedstep generate_cpu_entries() directly since the
cpu doesn't support speedstep.
For now the code is in the southbridge directory, but maybe it
should go into cpu/intel/ somewhere.
IIRC notebook cpus of the era can already have speedstep, so it
would probably be possible to pair the i82371eb with a
speedstep-capable cpu...
Also, I don't know if multiprocessor boards (abit bp6?) would need
to be handled differently.

Abuild-tested.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 0 insertions, 0 deletions

diff --git a/src/cpu/intel/car/Makefile.inc b/src/cpu/intel/car/Makefile.inc
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/cpu/intel/car/Makefile.inc
diff --git a/src/cpu/intel/car/disable_cache_as_ram.c b/src/cpu/intel/car/disable_cache_as_ram.c
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/cpu/intel/car/disable_cache_as_ram.c
diff --git a/src/cpu/intel/car/post_cache_as_ram.c b/src/cpu/intel/car/post_cache_as_ram.c
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/cpu/intel/car/post_cache_as_ram.c