From b672d94ce0199bc0bd882c61c7be9ac2c90eded5 Mon Sep 17 00:00:00 2001 From: Tobias Diedrich Date: Wed, 8 Dec 2010 21:40:12 +0000 Subject: Tobias Diedrich wrote: > Definitively a iasl problem, it can't even disassemble it's own > output back to something equivalent to the input file. > It seems to be generating Bytecode for the Add where it shouldn't. Here is a solution using the SSDT. Unfortunately iasl does not resolve simple arithmetic at compile time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the Processor statement. This patch instead dynamically generates the processor statement. I can't use the speedstep generate_cpu_entries() directly since the cpu doesn't support speedstep. For now the code is in the southbridge directory, but maybe it should go into cpu/intel/ somewhere. IIRC notebook cpus of the era can already have speedstep, so it would probably be possible to pair the i82371eb with a speedstep-capable cpu... Also, I don't know if multiprocessor boards (abit bp6?) would need to be handled differently. Abuild-tested. Signed-off-by: Tobias Diedrich Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/intel/car/Makefile.inc | 0 src/cpu/intel/car/disable_cache_as_ram.c | 0 src/cpu/intel/car/post_cache_as_ram.c | 0 3 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 src/cpu/intel/car/Makefile.inc create mode 100644 src/cpu/intel/car/disable_cache_as_ram.c create mode 100644 src/cpu/intel/car/post_cache_as_ram.c (limited to 'src/cpu/intel/car') diff --git a/src/cpu/intel/car/Makefile.inc b/src/cpu/intel/car/Makefile.inc new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/cpu/intel/car/disable_cache_as_ram.c b/src/cpu/intel/car/disable_cache_as_ram.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/cpu/intel/car/post_cache_as_ram.c b/src/cpu/intel/car/post_cache_as_ram.c new file mode 100644 index 0000000000..e69de29bb2 -- cgit v1.2.3